HT93LC46 1k 3-wire CMOS Serial EePROM Features. Operating voltage VCC Read: V~V Write: V~V Low power consumption Operating: 5mA max. HT93LC46 datasheet, HT93LC46 circuit, HT93LC46 data sheet: HOLTEK – CMOS 1K 3-Wire Serial EEPROM,alldatasheet, datasheet, Datasheet search site for. HT93LC46 datasheet, HT93LC46 circuit, HT93LC46 data sheet: HOLTEK – 1K 3- Wire CMOS Serial EEPROM,alldatasheet, datasheet, Datasheet search site for.
|Published (Last):||1 April 2016|
|PDF File Size:||18.44 Mb|
|ePub File Size:||14.36 Mb|
|Price:||Free* [*Free Regsitration Required]|
Since the internal auto-timing generator provides all timing signals for the write-all operation, so the SK clock is not required.
HT93LC46 데이터시트(PDF) – Holtek Semiconductor Inc
The auto-timing write cycle includes an automatic erase-before-write capability. No data can be written into the device in the programming disabled state. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise.
However, Holtek assumes no responsibility arising from the use of the specifications described. Taipei Sales Office 4F-2, No. The 8 bits or 16 bits data stream is preceded by a logical? Since the internal auto-timing generator provides all timing signals for the internal erase, so the SK clock is not required.
Stresses exceeding the range specified under?
HT93C56-A, HT93LC46, HT93LC46A
There is an internal pull-up resistor on the ORG pin. Its bits of memory are organized into 64 words of 16 bits each when ht93l4c6 ORG pin is connected to VCC or organized into words of 8 bits each when it is tied to VSS. After the write-all instruction set has been issued, the data writing is activated by the falling edge of CS.
The DO pin will remain low but when the operation is over, the DO pin will return to high and further instruction can be executed. By popular microcontroller, the versatile serial interface including chip select CS datasheet, serial clock Datashretdata input DI and data output DO can be easily controlled.
After the data word has been read the internal address will be automatically incremented by 1 allowing the next consecutive data word to be read out without entering further address data.
The following are the functional descriptions and timing diagrams of all seven instructions. The HT93LC46 contains seven instructions: The Ht93,c46 pin will remain low but when the operation is over, the DO pin will return to high and further instructions can be executed.
These are stress ratings only. Functional operation of this device at other conditions beyond those listed in the specification is not implied and adtasheet exposure to extreme conditions may affect device reliability. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. Since the internal auto-timing generator provides all timing signal for the erase-all operation, so the SK clock is not required.
After power on, the device is by default in the EWDS state. For successful instructions, CS must be low once after the instruction is ht93lc64. The data on DO pin changes during the low-to-high edge of SK signal. Test Conditions Input rise and fall time: Holtek reserves the right to alter its products without prior notification.
(PDF) HT93LC46 Datasheet download
These serial instruction data presented at the DI input will be written into the datashert at the rising edge of SK. The DO pin will datasheeh low but when the operation is over the DO pin will return to high and further instruction can be executed. When the user selectable internal organization is arranged into 64?
Since the internal auto-timing generator provides all timing signal for the internal writing, so the SK clock is not required.
At both the power on and power off state the device automatically entered the disable mode. The information appearing in this Data Sheet is believed to be accurate at the time of publication. For the most up-to-date information, please visit our web site at http: After the erase-all instruction set has been issued, the data erase feature is activated by the falling edge of CS. By so doing, the internal memory data can be protected.